industrial temperature range idt74alvcf162835a 3.3v cmos 18-bit universal bus driver with 3-state outputs 1 january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-4920/2 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ?v cc = 2.5v 0.2v ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? available in tssop and tvsop packages functional block diagram drive features: ? balanced output drivers: 18ma ? low switching noise applications: ? sdram modules ? pc motherboards ? workstations idt74alvcf162835a 3.3v cmos 18-bit universal bus driver with 3-state outputs description: this 18-bit universal bus driver is built using advanced dual metal cmos technology. data flow from a to y is controlled by the output-enable ( oe ) input. the device operates in the transparent mode when the latch-enable (le) input is high. the a data is latched if the clock (clk) input is held at a high or low logic level. if le is low, the a data is stored in the latch flip-flop on the low-to-high transition of clk. when oe is high, the outputs are in the high-impedance state. the alvcf162835a has series resistors in the device output structure which will reduce switching noise in 128mb and 256mb sdram modules. designed with a drive capability of 18ma, the alvcf162835a is a mid- way drive between the alvc162835 (12ma) and alvc16835 (24ma). the alvcf162835a is a faster version of the alvcf162835 or alvc162835. it is suitable for pc133 applications and particularly sdram modules clocked at 133 mhz. le a 1 to 17 other channels oe clk 27 54 28 30 1 d clk 3 y 1 c 1
industrial temperature range 2 idt74alvcf162835a 3.3v cmos 18-bit universal bus driver with 3-state outputs pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, 50 ma v i < 0 or v i > v cc i ok continuous clamp current, v o < 0 ?50 ma i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . pin names description oe 3-state output enable inputs (active low) clk register input clock le latch enable (transparent high) a x data inputs y x 3-state outputs pin description tssop/ tvsop top view gnd gnd gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 1 gnd gnd gnd 25 26 27 28 32 31 30 29 gnd nc a 1 nc nc y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 10 y 11 y 12 y 13 y 14 y 15 y 16 y 17 y 18 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 v cc a 16 a 17 a 18 gnd v cc clk gnd v cc v cc gnd oe le note: 1. as applicable to the device type. symbol parameter (1) conditions min. typ. max. unit c in input capacitance v in = 0v 4 5 6 pf c out output capacitance v out = 0v ? 7 9 pf c out i/o port capacitance v in = 0v ? 7 9 pf capacitance (t a = +25c, f = 1.0mhz) notes: 1. h = high voltage level l = low voltage level x = don?t care z = high-impedance = low-to-high transition 2. output level before indicated steady-state input conditions were established, pro- vided that clk is high before le went low. 3. output level before the indicated steady-state input conditions were established. function table (1) inputs outputs oe le clk ax yx hxxx z lhxl l lhxh h ll ll ll hh llhx y 0 (2) lllx y 0 (3)
industrial temperature range idt74alvcf162835a 3.3v cmos 18-bit universal bus driver with 3-state outputs 3 symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input high current v cc = 3.6v v i = v cc ?? 5a i il input low current v cc = 3.6v v i = gnd ? ? 5a i ozh high impedance output current v cc = 3.6v v o = v cc ?? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v ? 0.1 40 a i cch v in = gnd or v cc i ccz ? i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 750 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c note: 1. typical values are at v cc = 3.3v, +25c ambient. note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 1.9 ? i oh = ? 8ma 1.7 ? v cc = 2.7v i oh = ? 6ma 2.2 ? i oh = ? 12ma 2 ? v cc = 3v i oh = ? 8ma 2.4 ? i oh = ? 18ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 8ma ? 0.55 v cc = 2.7v i ol = 6ma ? 0.4 i ol = 12ma ? 0.6 v cc = 3v i ol = 8ma ? 0.55 i ol = 18ma ? 0.8
industrial temperature range 4 idt74alvcf162835a 3.3v cmos 18-bit universal bus driver with 3-state outputs operating characteristics, t a = 25c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 30 35 pf c pd power dissipation capacitance outputs disabled 12.5 14 notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction. switching characteristics (1) v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit f clock 150 ? 150 ? 150 ? m h z t plh propagation delay 1 4 ? 4.6 1 3.5 ns t phl ax to yx t plh propagation delay 1.3 5.5 ? 5.4 1.3 4.6 ns t phl le to yx t plh propagation delay 1.4 5.9 ? 5.6 1.4 3.5 ns t phl clk to yx t pzh output enable time 1.4 5.9 ? 6 1.1 5 ns t pzl oe to yx t phz output disable time 1 4.7 ? 4.6 1.3 4.2 ns t plz oe to yx t w pulse duration, le high 3.3 ? 3.3 ? 3.3 ? ns t w pulse duration, clk high or low 3.3 ? 3.3 ? 3.3 ? ns t su set-up time, data before clk 1.8 ? 1.5 ? 1 ? ns t su set-up time, data before le , clk high 1.9 ? 1.6 ? 1.5 ? ns t su set-up time, data before le , clk low 1.3 ? 1.1 ? 1 ? ns t h hold time, data after clk 0.6 ? 0.6 ? 0.6 ? ns t h hold time, data after le , clk high or low 1.4 ? 1.7 ? 1.4 ? ns t sk(o) output skew (2) ????? 500 ps switching characteristics from 0c to 65c, c l = 50pf v cc = 3.3v 0.15v symbol parameter min. max. unit t plh propagation delay 1.8 3.5 ns t phl clk to xyx
industrial temperature range idt74alvcf162835a 3.3v cmos 18-bit universal bus driver with 3-state outputs 5 open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v ol + v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v oh - v hz alvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 1.0mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 6 idt74alvcf162835a 3.3v cmos 18-bit universal bus driver with 3-state outputs ordering information idt xx alvc xxx xx package device type temp. range pa pf f162 74 thin shrink small outline package thin very small outline package 18-bit universal bus driver with 3-state outputs ? 40c to +85c xxxx family bus-hold 835 double-density with resistors, 18ma no bus-hold blank corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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